Method of switching video sources and computer system employing this method

ABSTRACT

A plurality of video devices, that is, a PC card controller  17,  an MPEG2 decoder  18,  a P1394 controller  20,  and a video capture  31  have each a motion-picture output port connected to a video/audio dedicated bus  4,  as well as an interface with a PCI bus  2.  Hence, any motion-picture source can be transferred directly to a display controller  14  through the video/audio dedicated bus, without using the PCI bus  2.  Various motion-picture sources can therefore be efficiently displayed.

TECHNICAL FIELD

The present invention relates to a computer system having a ZV (ZoomedVideo) port and also to a method of switching video sources to betransferred by using a ZV port.

BACKGROUND ART

In recent years, notebook-type personal computers have been used inincreasing numbers, each having a PC card socket which accords with thestandards of PCMCIA (Personal Computer Memory Card InternationalAssociation), an American association, and with the standards of JEIDA.Various techniques have been developed to use this PC card as a videocapture card or an MPEG decoder card, for controlling the input andoutput of motion-picture data.

System architecture having a PCI local bus is now used increasingly inorder to process a great amount of data, such as motion-picture data,with high efficiency. This is because the PCI local bus can transferdata at high speed.

If the PCI local bus is used, however, its data-transferring ability islimited. The data-transferring ability of the PCI local bus isinsufficient when the PC card is used as a video capture card or an MPEGdecoder card as is mentioned above.

Recently, a technique has been developed. The technique is to connect aPC card and a display controller directly, by a so-called ZV (ZoomedVideo) port, which is a bus designed exclusively for transferringmotion-picture data. The ZV port enables the PC card to outputvideo/audio data directly to the display controller/audio controller,without using the system bus. This solves the problem that the systembus is occupied for a long time to transfer a great amount of videodata, thereby enhancing the video-data processing ability of the system.

Recently, multimedia techniques have advanced also in the field ofpersonal computers. Various devices other than PC cards, which handlemotion-picture data, are now incorporated in the system. These deviceswill be exemplified as follows:

(1) Video capture: Converting analog video signals from an imagingdevice such as a video camera to digital data, and inputting the digitaldata.

(2) MPEG decoder: Expanding motion-picture data compressed by MPEG, thusgenerating live motion-picture data.

(3) High-speed serial interface, e.g. IEEE1394: Inputting motion-picturedata transferred from a digital video camera, a digital video player,and the like.

These devices are connected to the system bus in most cases. Therefore,the motion-picture data output from these devices will be transferred tothe display controller through the system bus.

(1) Usually, the system bus has a bandwidth large enough to transfermotion-picture data. The rate of transferring motion-picture data musttherefore be lowered in order to transfer motion-picture data throughthe system bus. If the transfer rate is lowered, the resolution of themotion picture will decrease, the frame rate thereof will decrease, orthe number of bits per pixel will decrease. Consequently, the motionpicture will be deteriorated in quality.

(2) The motion-picture data transfer mostly occupies the bandwidth ofthe system bus. The operations other than the motion-picture transfervia the system bus, for example the data transfer between the device anda disk drive will become slow. Further, the device may not normallyoperate, failing to transfer data in real-time fashion. If acommunication device such as a modem does not operate normally, forexample, a part of data may not be transmitted.

DISCLOSURE OF INVENTION

The present invention has been made in view of the foregoing. Its objectis to provide a computer system in which a plurality of video sourcescan be transferred directly to the display controller, without using thesystem bus, from a plurality of devices which process motion-picturedata, so that the various video sources can be displayed with highefficiency, and also to provide a method of switching video sources inthe system.

The present invention is a computer system having a display controllerhaving a video port for receiving motion-picture data and capable ofdisplaying the motion-picture data input to the video port, and amotion-picture data bus provided for transferring exclusively themotion-picture data to the video port of the display controller. Thecomputer system is characterized by comprising a plurality of videodevices and switching means. The video devices process differentmotion-picture sources, each having an output port connected to themotion-picture data bus and designed to output motion-picture data fromthe output port to the motion-picture data bus. The switching meansswitches the video devices, thereby selecting one video device which isto transfer motion-picture data to the display controller through themotion-picture data bus.

In the computer system, the video devices, such as a video capture, anMPEG decoder, and an IEEE1394 serial interface, are connected to avideo/audio dedicated bus provided for transferring motion-picture datadirectly to the video port (ZV port) of the display controller, withoutusing the system bus. Thus, one and the same video/audio dedicated busis used to transfer motion-picture data from whichever video device.Therefore, whichever video source can be transferred to the displaycontroller, without using the system bus. The various video sources canbe transferred with high efficiency. Furthermore, the computer systemhas switching means for switching the video devices which use thevideo/audio dedicated bus. The switching means operates such thatmotion-picture data is transferred to the display controller from onlyone device at a time. This makes it possible for the single video/audiodedicated bus to connect the devices to the display controller in apoint-to-point fashion. Data collision on the video/audio dedicated buscan thereby be prevented.

The means for switching the video devices, thus enabling one device at atime to use the video/audio dedicated bus, preferably has one of thefollowing alternative structures:

(1) Each video device has an output buffer for outputting motion-picturedata from the output port to the video/audio dedicated bus. Each videodevice also has means for enabling or disabling the output buffer tooutput the data, in accordance with an instruction supplied from the CPUof the computer system.

Each video device therefore outputs motion-picture data to thevideo/audio dedicated bus only when the CPU issues a motion-picture datatransfer instruction or the like. Software executed by the CPU enablesthe output buffer of only one video device, at a time, to output data.Data collision on the video/audio dedicated bus can therefore beprevented easily.

(2) The video devices are connected to the video/audio dedicated bus,forming a daisy chain. A control signal line is added for transferringan enable signal which allows each video device to use the video/audiodedicated bus, to the video devices, one after another, first from thevideo device which located at the head of the daisy chain.

Each video device has an output buffer for outputting motion-picturedata from the output port to the video/audio dedicated bus. Each videodevice also has means for enabling or disabling the output buffer tooutput the data, in accordance with an instruction supplied from the CPUof the computer system and the enable signal transferred through thecontrol signal line. The means inhibits the transfer of the enablesignal to the next video device when the output buffer is enabled tooutput the motion-picture data.

In this structure, any video device has priority over the video devicelocated downstream of the daisy chain, with regard to the use of thevideo/audio dedicated bus. No enable signal is transferred to the videodevice located downstream of the daisy chain before the audio deviceenabled to use the video/audio dedicated bus finishes using thevideo/audio dedicated bus. Thus, automatic control is achieved that theoutput buffer of only one device is allowed, at a time, to output data.Software control is unnecessary to allow, at a time, the output bufferof only one device to output data.

(3) A plurality of video devices are connected to the video/audiodedicated bus. A control signal line is added which is set into anactive state by any video device which is requesting for the use of thevideo/audio dedicated bus.

Each video device has an output buffer for outputting motion-picturedata from the output port to the video/audio dedicated bus. Each videodevice also has two means. The first means sets the control signal linein the active state for a prescribed period, in accordance with amotion-picture data transfer instruction issued from the CPU of thecomputer system, and allows the output buffer to output motion-picturedata upon lapse of the prescribed period. The second means monitors thestate the control signal line assumes, and prohibits the output bufferfrom outputting motion-picture data, as long as the control signalremains active.

In this structure, the video device, which has last set the controlsignal line into the active state gains priority over any other videodevice with regard to the use of the video/audio, dedicated bus.Therefore, priority can be equally assigned to any device at the initialstage of operation.

(4) A means which can use the video/audio-dedicated bus is added to thestructure described in the paragraph (3). The means monitors the statusthe control signal line takes. When a motion-picture data transferinstruction is issued while the control signal remains active, the meanssustains an operation of setting the control signal line into an activestate until the control signal line is released from the active state.The video device, which has last received a motion-picture data transferinstruction from the CPU, is allowed to use the video/audio-dedicatedbus.

(5) In the structure specified in the paragraph (3), the period forwhich the control signal line remains in the active state in accordancewith a motion-picture data transfer instruction supplied from the CPU isdifferent for each video device. The structure specified in theparagraph (4) may be added to this structure. If so, any device having asmall pulse width can have priority with regard to the use of thevideo/audio dedicated bus, even if it receives a motion-picture datatransfer instruction after any other device that has a great pulsewidth.

(6) Software executes the following sequence of operations. First, thestates in which the video devices use the video/audio-dedicated bus aremanaged. In response to a request for the video/audio-dedicated bus,supplied from a driver program which controls the video devices, it isdetermined which video device is using the video/audio-dedicated bus.Next, communication is performed with the video device now using thevideo/audio-dedicated bus, thereby determining whether or not the videodevice can release the video/audio dedicated bus. If it is found thatthe device can release the bus, use permission is supplied to the.driver program which has issued the request for the video/audiodedicated bus request.

In this sequence of operations, the states in which the video devicesuse the video/audio-dedicated bus are managed under the control ofsoftware. Communication is effected between the software and the driverprograms which control the video devices, thereby switching one devicefor another. Hence, motion-picture data is transferred to the displaycontroller from only one device at a time.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a block diagram showing a computer system according to oneembodiment of the present invention.

FIG. 2 is a block diagram showing in detail the connection between thevideo capture and video capture controller illustrated in FIG. 1.

FIG. 3 is a diagram explaining the principle of switching devices, forconnecting one of the devices to the video/audio dedicated bus providedin the system.

FIG. 4 is a diagram illustrating the internal structures of deviceswhich are switched in a first switching control mode to be connected tothe video/audio dedicated bus in the system.

FIG. 5 is a diagram depicting the combinatorial logic circuitsincorporated in devices which are switched in a second switching controlmode to be connected to the video/audio dedicated bus in the system.

FIGS. 6A and 6B are diagrams representing the input-output relations ofthe combinatorial logic circuits shown in FIG. 5.

FIG. 7 is a circuit diagram showing an example of the combinatoriallogic circuits shown in FIG. 5.

FIG. 8 is a diagram depicting the combinatorial logic circuitsincorporated in devices which are switched in a second switching controlmode to be connected to the video/audio dedicated bus in the system.

FIG. 9 is a circuit diagram depicting an example of the combinatoriallogic circuits shown in FIG. 8.

FIGS. 10A to 10E are a timing chart explaining the operation of thecombinatorial logic circuits shown in FIG. 8.

FIG. 11 is a diagram showing the combinatorial logic circuitsincorporated in devices which are switched in a third switching controlmode to be connected to the video/audio dedicated bus in the system.

FIGS. 12A to 12C are a chart explaining how the programmable pulsegenerating circuit provided in each combinatorial logic circuit shown inFIG. 11 generates pulses having a width specific for the deviceincorporating the logic circuit.

FIGS. 13A to 13H are a timing chart explaining the operation of thecombinatorial logic circuits shown in FIG. 11.

FIG. 14 is a diagram illustrating the software configuration which isused to switch the devices in a fourth switching control mode in thesystem.

FIG. 15 is a flow chart explaining how the devices are switched to beconnected to the video/audio dedicated bus, by means of the softwareshown in FIG. 14.

FIG. 16 is a diagram illustrating another software configuration whichis used to switch the devices in a fourth switching control mode in thesystem.

BEST MODE OF CARRYING OUT THE INVENTION

Embodiments of the present invention will now be described, withreference to the accompanying drawings.

FIG. 1 illustrates a computer system according to an embodiment of theinvention. The computer system is a notebook- or laptop-type portablecomputer which can be battery-driven. The system has a system board, onwhich there are mounted a CPU bus 1, a PCI bus 2, a MINI-ISA bus 3, anda video/audio dedicated bus 4. The MINI-ISA bus 3 has a simplified busstructure, or is an ISA bus excluding some specified signal lines. Thevideo/audio dedicated bus 4 connects a PC card socket 171 or 172, adisplay controller (VGA controller) 14 and a sound controller 41 in apoint-to-point fashion.

The video/audio-dedicated bus 4 incorporates a video bus and an audiobus. The video bus comprises a YUY data signal line (for supplying 8-bitluminance data Y and 8-bit color-difference data UV), and signal linesfor supplying horizontal and vertical sync signals (HREF, VSYNC) andpixel clock signals (PCLK).

An audio bus comprises signals lines including a line for supplying PCMsignals for serially transferring audio data, a line for supplying asignal (LRCK) indicating whether the right- or left-channel audio datais being output, and a line for transferring a serial clock signal.

Also mounted on the system board are: a CPU 11, host/PCI bridge device12, main memory 13, display controller (VGA controller) 14, I/O controlgate array 16, PC card controller 17, MPEG2 decoder 18, video capturecontroller 19, IEEE1394 controller 20, modem 21, USB (Universal SerialBus) controller 22, video capture 31 and sound controller 41.

Of these devices, the PC card controller 17, MPEG2 decoder 18, IEEE1384controller 20 and video capture controller 19 (video capture 31) aredevices which handles motion-picture data. Their motion-picture outputports are connected in common to the video/audio dedicated bus 4 so asto transfer motion-picture data to the display controller 14 through thevideo/audio dedicated bus 4.

The CPU 11 is, for example, a microprocessor “Pentium” manufactured andsold by Intel Inc., U.S.A. The CPU bus 1, which is connected to theinput/output pins of the CPU 11, has a 64-bit data bus.

The main memory 13 is a memory device for storing operating systems,device drivers, application programs to be executed, and data to beprocessed. The memory 13 comprises a plurality of DRAM modules. Thememory 13 is composed of a system memory and an extended memory. Theextended memory has been mounted on the system board, as is needed, bythe user. The DRAM modules constituting the system memory and extendedmemory are synchronous DRAMs or Rambuses.

The host-PCI bridge device 12 is provided between the CPU bus 1 and theinternal PCI bus 2 has functions. One function is to convert a bus cycleincluding data and addresses in two directions. Another function is toachieve the access control of the main memory 13 via a memory bus.

The PCI bus 2 is a clock-synchronous input/output bus. All cycle on thePCI bus 2 is effected in synchronism with a PCI bus clock signal. ThePCI bus clock signal has a maximum frequency of 33 MHz. The PCI bus 2has an address/data bus which is used in time-division scheme. Theaddress/data bus has a 32-bit width.

The data-transfer cycle on the PCI bus. 2 consists of an address phaseand at least one data phase which follows the address phase. In theaddress phase, an address and a transfer type are output. In the dataphase, 8-bit data, 16-bit data, 24-bit data or 32-bit data is output.

Like the host/PCI bridge device 12, the display controller (VGAcontroller) 14 is one of the bus masters for the PCI bus 2. It isprovided to display the image data stored in a video memory (VRAM) 143on a LCD 144 or an external CRT display. It serves to display VGA-typetexts and graphics.

The display controller 14 has a video port (ZV port) 141 which isconnected to video/audio dedicated bus 4 as is illustrated in thefigure. The controller 14 has a function of displaying a motion-picturedata stream S1 input to the video port 141, as a video window, on adisplay screen.

The I/O control gate array 16 is a one-chip LSI capable of performing aplurality of I/O control functions. In the present embodiment, the array17 incorporates an infrared-ray controller 161, an IDE controller 612, areal-time clock (RTC) 163, and an I/O controller 164. The infrared-raycontroller 161 controls infrared-ray communication between the array 16and an external infrared-ray communications device. The IDE controller162 controls devices having IDE (Integrating Drive Electronics) or anATAPI (ATA Packet Interface), such as a hard disk drive, a CD-ROM driveand a DVD-ROM drive. The I/O controller 164 controls a printer port, aserial port (SIO) and a floppy disk drive (FDD) and also controlsISA-compatible devices such as the sound controller 41 provided on theMINI-ISA bus 3.

The PC card controller 17 is a PCI device. It controls a 16-bit PC cardof PCMCIA specification and a 32-bit PC card of card-bus specification,under the control of the CPU 11. It serves to transfer motion-picturedata through the video/audio-dedicated bus 4. The PC card controller 17has two operating modes, i.e. normal mode and multimedia mode (ZV portmode). In the normal mode, the controller 17 controls ordinary PC cardssuch as a modem card, to transfer data between the PCI bus 2 and anordinary PC card, using neither the video/audio dedicated bus 4 nor theZV port 141.

The PC card controller 17 operates in the multimedia mode (ZV port mode)when PC cards processing motion-picture data, such as a video capturecard, an MPEG2 encoder card and an MPEG2 decoder card, are set in the PCcard sockets 171 and 172. In this mode, the video/audio-dedicated bus 4is used, and a motion-picture data stream S4 is transferred from a PCcard directly to the display controller 14 through the video/audiodedicated bus 4 and the ZV port 141.

It is the CPU 11 which switches the operating mode, from the normal modeto the multimedia mode, or vice versa. More precisely, the CPU 11 readsattribute data from the PC card set in a PC card socket and determinesthe type of the PC card from the attribute data. If the CPU 11determines that the PC card is of a type, which accords with themultimedia mode, it sets the PC card controller 17 into the multimediamode. Such switching to the multimedia mode is detailed in U.S. patentapplication Ser. No. 08/687,371 (PCT Application PCT/JP96/00111 filedJan. 23, 1996, put into the U.S. national phase on Aug. 2, 1996;Inventor: Hiroki Zenda), the assignee of which is identical to theassignee of the present application.

The sound controller 41 controls the inputting and outputting of audiodata under the control of the CPU 11. The controller 41 has the functionof performing A/D conversion on the audio signals supplied from amicrophone terminal and storing the digital data into the memory 13. Italso has the function of converting digital data transferred through thevideo/audio dedicated bus 4 to analog signals and output these analogsignals to a loudspeaker.

The MPEG2 decoder 18 has a PCI interface and a motion-picture outputport which are connected to the PCI bus 2 and the video/audio dedicatedbus 4, respectively. The MPEG2 decoder 18 receives via the PCI bus 2 themotion-picture data output from, for example, a DVD-ROM drive andconverted to digital compressed codes by MPEG2, and then decodes thecodes into motion-picture data. The motion-picture data thus obtained isconverted to a motion-picture data stream S2 of 16-bit YUV data format.The data stream S2 is output onto the video/audio dedicated bus 4 andtransferred to the video input port (ZV port) 141 of the displaycontroller 14.

In an MPEG2 data stream read from a DVD-ROM drive, encoded data itemsrepresenting main images (video) of movie or the like, sub-images(sub-pictures) such as subtitles, and audio signals are multiplexed. Thesub-images are encoded by run-length encoding, and the audio signals areencoded by the Dolby Digital system. It is therefore desired that theMPEG2 decoder 18 incorporate three decoders and that these decoders beoperated simultaneously to decode DVD video data including such threedata streams of different types. The three decoders are an MPEG2 decoderfor decoding main picture data, a sub-capture decoder for decodingsub-picture data, and an audio decoder for decoding audio signals. Thevideo data decoded by the MPEG2 decoder and the sub-picture data decodedby the sub-picture capture decoder are synthesized into data of 16-bitYUV data format, which is output onto the video bus included in thevideo/audio dedicated bus 4. The audio signals decoded by the audiodecoder are transferred in a serial data transfer format through theaudio bus included in the video/audio-dedicated bus 4.

The video capture controller 19 transfers the video data acquired fromthe video capture 31 either to the video port 141 via the video/audiodedicated bus 4, or to the main memory 13 through the PCI bus 2, inaccordance with an instruction supplied from the CPU 11. That is, asshown in FIG. 2, the video data output through a capture I/F 131 isfirst stored in a buffer circuit 193 provided in the video capturecontroller 19, and then fetched into a capture controller 191. Thecapture controller 191 outputs the video data to the video/audiodedicated bus 4 via a buffer circuit 195 if the controller 191 is soinstructed by the CPU 11. The video capture controller 19 controls thevideo capture 31 in accordance with instructions supplied through an I2Cbus.

If instructed by the CPU 11 to output the video data to the PCI bus 2,the capture controller 191 outputs the video data to the PCI bus 2through the buffer circuit 197. To transfer motion-picture data form thevideo/audio dedicated bus 4 to the main memory 13, the scalerincorporated in the controller 191 performs a scale-down process on themotion-picture data, thereby decreasing the data transfer rate as isrequired in view of the band width of the PCI bus 2.

(The scale-down process includes changing of the frame rate andresolution, converting the color format, and the like.) Themotion-picture data thus processed is stored into a FIFO buffer. Thedata in the FIFO buffer is transferred to the main memory 12 by means ofDMA transfer.

The IEEE1394 controller 20 is provided to control data transfer betweenthe computer system and an external apparatus, which is achieved throughan IEEE1394 high-speed serial interface. The controller 20 has a PCIinterface and a motion-picture output port. The PCI interface isconnected to the PCI bus 2, and the motion-picture output port to thevideo/audio dedicated bus 4. Upon receipt of motion-picture data from adigital video camera or the like via the IEEE1394 high-speed serialinterface, the IEED1394 controller 20 converts the motion-picture datato a motion-picture data stream S5 of 16-bit YUV data format. The datastream S5 is transferred to the display controller 14 through the videobus included in the video/audio dedicated bus 4.

The video capture 31 is connected to the video/audio dedicated bus 4(and the video port 141) by the video capture controller 19. The videocapture 31 receives motion-picture data input from a video camera, animage sensor or the like through a camera interface, and converts thedata to a motion-picture data stream S3 of 16-bit YUV data format. Thedata stream S3 is transferred to the display controller 14 under thecontrol of the video capture controller 19 as described above.

In the system shown in FIG. 1, a plurality of video devices which handlemotion-picture data items of different type, i.e. the PC card controller17, MPEG2 decoder 18, IEEE1394 controller 20 and video capture 31, havea motion-picture output port each, in addition to an interface connectedto the PCI bus 2. The motion-picture output port is connected to thevideo/audio-dedicated bus 4. Therefore, various motion-picture sourcescan be transferred to the display controller 14, directly via thevideo/audio-dedicated bus 4, without using the PCI bus 2. Hence, variousvideo sources can be displayed with high efficiency.

The video/audio-dedicated bus 4 can transfer but only one motion-picturedata item at a time. The present system therefore incorporates a controlunit for controlling the switching of motion-picture sources. Thecontrol unit selects the PC card controller 17, the MPEG2 decoder 18,the P1394 controller 20, or the video capture controller 19 (videocapture 31) and connects the device selected to the video/audiodedicated bus 4. Thus, only one device uses the video/audio-dedicatedbus 4 at a time.

Some devices for controlling the switching of motion-picture sourceswill be explained below.

(1) The first control device will be described, with reference to FIGS.2 to 4.

As shown in FIG. 3, a selector is provided for selecting themotion-picture output port of the PC card controller 17, MPEG2 decoder18, IEEE1394 controller 20 or video capture controller 19. Themotion-picture output port, thus selected, is connected to thevideo/audio dedicated bus 4. Motion-picture data can therefore betransferred to the display controller 14, but from only one device at atime. Namely, one video/audio dedicated bus 4 can connect the PC cardcontroller 17, MPEG2 decoder 18, IEEE1394 controller 20 and videocapture controller 19 can be connected in point-to-point fashion. Thisprevents collision of. data on the video/audio-dedicated bus 4.

The selector comprises 3-state output buffers 101, 102, 103 and 104. Thebuffers 101 to 104 are connected at input, respectively to themotion-picture output ports of the PC card controller 17, MPEG2 decoder18, IEEE1394 controller 20 and video capture controller 19, and atoutput to the video/audio dedicated bus 4. The buffers 101 to 104receive, respectively, four enable/disable signals (EN/DIS1, EN/DIS2,EN/DIS3 and EN/DIS4) which can be controlled by a command from the CPU11. Each 3-state output buffer outputs or does not output motion-picturedata to the bus 4, in accordance with the enable/disable signal it hasreceived.

When this control device is used, each video device outputsmotion-picture data to the video/audio dedicated bus 4 only if thecommand supplied from the CPU 11 enables it to transfer themotion-picture data.

That is, the software the CPU 11 executes allows the output buffer ofonly one device, at a time, to output the motion-picture data. Datacollision on the video/audio-dedicated bus 4 can be thereby prevented.Further, all output buffers except the one enabled to output data areelectrically isolated from the video/audio dedicated bus 4 since theyare disabled, or set in a high-impedance output state.

As FIG. 4 shows, the selector shown in FIG. 3 has, besides the 3-stateoutput buffers 101, 102, read/write registers 201, 202, . . . which arecontrolled by the CPU 11 to store and output data. When the enable flagF1 of, for example, the register 201 is set, the enable/disable signalEN/DIS1 supplied to the 3-state output buffer 101 becomes active. Thedevice 1 can then transfer motion-picture data through thevideo/audio-dedicated bus 4.

(2) The second control device will be described, with reference to FIGS.5, 6A, 6B and 7.

As can be seen from FIG. 5, the order in which the devices are to usethe video/audio dedicated bus 4 is automatically determined by means ofhardware control. More specifically, one ZV enable signal line isconnected to the video/audio dedicated bus 4. The ZV enable signal lineconnects a plurality of devices (i.e. PC card controller 17, MPEG2decoder 18, P1394 controller 20 and video capture controller 19),forming a daisy chain. The ZV enable signal line is provided to transfera ZV enable signal sequentially to the devices, first to the device atthe head of the daisy chain and finally to the device at the endthereof. The ZV enable signal enables any device to use thevideo/audio-dedicated bus 4.

The devices have combinatorial logic circuits 301, 302, . . . ,respectively, in addition to 3-state output buffers 101, 102, . . . andregister 201, 202, . . . The combinatorial logic circuits 301, 302, . .. generates a ZV enable/disable signal on the basis of the enable flagF1 set by the CPU 11 and the ZV enable signal transferred through the ZVenable signal line. Each of the combinatorial logic circuits has aninput terminal A, a ZV enable signal input terminal X, an enable/disablesignal output terminal Z, and a ZV enable signal output terminal Y. Theinput terminal A receives the enable flag F1. A ZV enable signal isoutput from the ZV enable signal output terminal Y to the next device.

FIG. 6A is a truth table showing the values the output Y may have inaccordance with the inputs X and A. FIG. 6B is a truth tablerepresenting the values the output Z may have in accordance with theinputs X and A.

If input X=1 (if the ZV enable signal input is active) when input A=1(when the enable flag F1 is set, indicating that motion-picture data canbe transferred), output Z=1, enabling the output buffer. In this case,output Y=0, and the transfer of the ZV enable signal to the next deviceis stopped. When input A=0 (when the enable flag F1 is not set,indicating that motion-picture data cannot be transferred), the input Xremains unchanged and becomes the output Y. If input X=0, outputs Y andZ are 0, regardless of the value of input A.

Each of the combinatorial logic circuits 301 and 302 can comprise two2-input NAND gates 401 and 402, an inverter 403 and an input buffer 404,as is shown in FIG. 7.

The more upstream the device is located in the daisy chain, the higherpriority it has to use the video/audio dedicated bus 4. (Here, thedevice 1 is located at the most upstream position.) The ZV enable signalis not transferred to any device located downstream of the deviceallowed to use the video/audio dedicated bus 4, until the devicefinishes using the video/audio dedicated bus 4. Therefore, automaticcontrol is achieved to allow, at a time, only the output buffer of onlyone device to operate. The input X to the most upstream device is alwaysset at the value of “1.”

(3) The third control device will be described, with reference to FIGS.8 and 9 and FIGS. 10A to 10E.

As shown in FIG. 8, the video/audio-dedicated bus 4 includes anadditional ZV control signal line. This signal line is connected incommon to all devices. The ZV control signal line is provided to supplya signal indicating that one device is requesting for the use of thevideo/audio dedicated bus 4, to all other devices. The signal line isactivated for a predetermined period by the device which is requestingfor the use of the video/audio-dedicated bus 4.

The devices have combinatorial logic circuits 501, 502, . . . ,respectively, in addition to 3-state output buffers 101, 102, . . . andregister 201, 202, . . . . Each of the combinatorial logic circuits 501,502, . . . renders the ZV control signal line active for thepredetermined period, in response to the enable flat F1 set by a commandsupplied from the CPU 11. Upon lapse of the predetermined period, thecombinatorial logic circuit sets the output buffer into an active state.Further, it monitors the state of the ZV control signal line andmaintains the output buffer in disabled state while the ZV controlsignal line remains active.

As shown in FIG. 9, each of the combinatorial logic circuits 501, 502, .. . comprises a pulse generating circuit 601, a delay circuit 602, aflip-flop 603, a ZV control signal output buffer 604, and a AV controlsignal output buffer 605.

The operation of each of the combinatorial logic circuits shown in FIG.9 will be explained, with reference to the timing chart of FIGS. 10A to10E. Here it is assumed that the enable flag F1 is set in the register201 of the device 1 while the output buffer 102 of the device 2 remainsenabled.

In the device 1, the pulse generating circuit 601 outputs a one-shotpulse signal ZV-EN1 when the enable flag F1 is set. The one-shot pulsesignal ZV-EN1 is supplied to the delay circuit 602. It is also supplied,as a ZV control signal, onto the ZV control signal line through thebuffer 604. The combinatorial logic circuits of all devices monitor thechange in the ZV control signal, which takes place at this time. In thedevice 1, the flop-flop 603 is reset. In the device 2, the flip-flop isreset, too. The enable/disable signal EN/DIS2 is thereby disabled.

Upon lapse of the time corresponding to the width of the one-shot pulsesignal ZV-EN1, the display circuit 602 outputs a set signal SET1. Theset signal SET1 is supplied to the flip-flop 603. The flip-flop 603changes the enable/disable signal EN/DIS1 to 1, or activates the signalEN/DIS1, in response to the set signal SET1.

Thus, the output buffers of all devices are disabled by using the ZVcontrol signal line. Then, only the device that has last activated theZV control signal line by enabling the output buffer is allowed to usethe video/audio-dedicated bus 4. Hence, priority can be equally assignedto any device at the initial stage of operation.

(4) The fourth control device will be described, with reference to FIG.11, FIGS. 12A to 12C and FIGS. 13A to 13H.

The combinatorial logic circuits shown in FIG. 11 are modifications ofthe combinatorial logic circuits explained with reference to FIG. 9.That is, a programmable pulse generating circuit 701 and a programmabledelay circuit 702 are used in place of the pulse generating circuit 601and the delay circuit 602, respectively. The circuit 701 can generate apulse. whose width can be programmable by the CPU 11. The circuit 702can delay an input signal by any time programmable by the CPU 11.Furthermore, each combinatorial logic circuit comprises an additionalcomponent, i.e. an AND gate 703.

The width of the pulse signal generated from the programmable pulsegenerating circuit 701 is initially set at a different value for eachdevice, as is illustrated in FIGS. 12A to 12C. Similarly, the delay timeof the programmable delay circuit 702 is initially set at a differentvalue for each device.

Thus, even if the enable flag is set in two or more devices at the sametime, only the device to which the longest pulse width is allocated isallowed to use the video/audio-dedicated bus 4. Data collision on thevideo/audio-dedicated bus 4 can be thereby prevented.

The ZV control signal may be active when the ZV enable flag is set. Inthis case, the AND gate 703 prevents the circuit 701 from generating apulse signal ZV-EN1, until the ZV control signal line is released fromthe active state.

The device in which an enable flag has been most recently set from theCPU 11 can therefore be allowed to use the video/audio-dedicated bus 4.Should an enable flag be set in a first device whose pulse width isshort immediately after an enable flag is set in a second device whosepulse width is longer, the first device is allowed to use thevideo/audio-dedicated bus 4 prior to the second device.

The operation of each of the combinatorial logic circuits shown in FIG.11 will be explained, with reference to the timing chart of FIGS. 13A to13H. Here it is assumed that the enable flag F1 is set simultaneously inthe devices 1 and 2 while the output buffer 103 of the device 3 remainsenabled.

In the device 1, the pulse generating circuit 701 outputs a one-shotpulse signal ZV-EN1 when the enable flag F1 is set while the ZV controlsignal remains at the value of 0. At the same time, the device 2 outputsa one-shot pulse signal ZV-EN2. These pulse signals change the potentialof the ZV control signal, whereby the flip-flops of all devices arereset. Therefore, in the device 3, the enable/disable signal EN/DIS3 isswitched into a disabled state.

In the device 2, a set signal SET2 is output upon lapse of the timecorresponding to the pulse width of the one-shot pulse signal ZV-EN2.The set signal SET2 is supplied to the flip-flop. However, the setsignal SET2 is masked, because the one-shot pulse signal ZV-EN1 is stillbeing output at this time. The flip-flop has yet to be set.

In the device 1, a set signal SET1 is output upon lapse of the timecorresponding to the pulse width of the one-shot pulse signal ZV-EN1. Atthis time, the one-shot pulse signal ZV-EN2 has not been generated.Therefore, the flip-flop 603 sets the enable/disable signal EN/DIS1 atthe value of 1, in accordance with the set signal SET1. In other words,it renders the signal EN/DIS1 active.

(5) The fifth control device will be described, with reference to FIGS.14 and 15.

Here it will be explained how a control device of the type described inthe paragraphs (1) switches the devices by means of software control sothat only one device may use, at a time, the video/audio-dedicated bus4. FIG. 14 represents the configuration of the software designed toswitch the devices in such a manner.

FIG. 14 shows various programs. The video/audio-dedicated bus manager isa program designed to manage the use of the video/audio-dedicated bus 4.The application programs 1, 2 and 3 cause devices 1, 2 and 3,respectively, to use the video/audio-dedicated bus 4 in order to displaymotion pictures. The video/audio-dedicated bus client drivers 1, 2 and 3are driver programs for controlling the devices 1, 2 and 3,respectively.

The video/audio-dedicated bus manager has the function of communicatingwith the video/audio-dedicated bus client drivers 1, 2 and 3. Using thisfunction, it switches the right to the use of the video/audio-dedicatedbus 4 among the devices, as will be briefly described below.

Assume that the video/audio-dedicated bus client driver 1 issues arequest for the use of the video/audio-dedicated bus 4. Then, thevideo/audio-dedicated bus manager refers to the management table T1which manages, for each device, the use of the video/audio-dedicated bus4, thereby determining which device is now using thevideo/audio-dedicated bus 4. The manager supplies a signal to thevideo/audio-dedicated bus client driver associated with the device whichis using the bus 4 (e.g., the video/audio-dedicated bus client driver3). This signal shows that one of the other client drivers has issued arequest for the use of the video/audio-dedicated bus 4. The manager thensupplies a signal to the client driver 1 which has issued the request,said signal indicating whether the right to use the bus 4 can beswitched or not. If the signal shows that the right to use the bus 4 canbe switched, the manager rewrites the management table T1 and switchesthe right to use the video/audio-dedicated bus 4. The right to use thebus 4 can be switched by setting the enable flag in the device which isto use the video/audio-dedicated bus 4 and resetting the enable flag inthe device which is to release the right to use the bus 4. Thevideo/audio-dedicated bus client driver associated with the device whichis to use the video/audio-dedicated bus 4 effects the setting andresetting of the enable flag.

The sequence of operations for switching the right to use the bus 4 willbe explained, with reference to the flow chart of FIG. 15.

When the operating system is activated or when a PC card or the likewhich can use the bus 4 is inserted into or pulled from a card socket,the video/audio-dedicated bus manager counts devices which areincorporated in the computer system and which can use the bus 4. Themanager also prepares the management table T1, which manages, for eachdevice, the use of the video/audio-dedicated bus 4 (Step S101).

If the devices are ISA devices, particularly PNPID devices and PCIdevices, the manager counts these devices in the following way. First,the manager refers to the information (INF) file. Next, it checks thedevice IDs, vender IDs and subsystem device IDs included in theinformation file, thereby counting the devices. If ZV device informationis found in the INF file, the manager writes the ZV device informationin the OS registry. In this case, the manager refers to the informationin the registry, thereby counting the devices.

A PC card may be inserted to the card socket while the system isoperating. If so, the drivers of socket service driver and card service,both shown in FIG. 16. The drivers supply a signal indicating theinsertion, to the video/audio-dedicated bus manager. In response to thesignal, the video/audio-dedicated bus manager determines, from theattribute information of the card, whether or not the card can use thevideo/audio-dedicated bus. If the card is found to be capable of usingthe bus 4, it suffices to add the device to the management table T1.When the PC card is pulled from the card socket while the system isoperating, the manager determines, from the ID number or attributeinformation of the card socket, whether or not the card has been countedas one that can use the video/audio-dedicated bus 4. If the card isfound to have been so counted, it suffices to delete the device from themanagement table T1.

When an application is executed, which involves the transfer ofmotion-picture data through the video/audio-dedicated bus 4, theapplication loads the corresponding video/audio-dedicated client driverinto the main memory 13 (Step S102). The video/audio-dedicated clientdriver, thus loaded, issues a request for the bus 4 to thevideo/audio-dedicated bus manager (Step S103). The video/audio-dedicatedbus manager refers to the management table T1, determining whether ornot any other device is using the video/ audio-dedicated bus 4 (StepS105).

If no device is using the video/ audio-dedicated bus 4, thevideo/audio-dedicated bus manager issues use permission to thevideo/audio-dedicated bus client driver which has made a request for thebus 4 (Step S106). Upon receipt of the use permission, thevideo/audio-dedicated bus client driver sets an enable flag in theregister of the associated device. The output buffer of the device isthereby set into operable state (Step S107). At this time,video/audio-dedicated bus manager writes data showing that the device isusing the video/audio-dedicated bus, in that part of the managementtable T1 which is assigned to the device.

If any device is using the video/audio-dedicated bus 4, thevideo/audio-dedicated bus manager identifies the device. The managerthen supplies a signal to the video/audio-dedicated bus client driverassociated with the device, said signal indicating that anothervideo/audio-dedicated bus client driver has issued a request for thevideo/audio-dedicated bus 4 (Steps S108 and S109). Upon receipt of therequest for the bus 4, the video/audio-dedicated bus client driveranswers whether or not the right to use the video/audio-dedicated bus 4can be switched.

For example, a video/audio-dedicated bus client driver associated withan application which display and record a motion pictures by using thevideo capture 31 may reject the request for switching the right to usethe bus 4 in order to prevent an interruption of recording of the motionpicture. If this is the case, the video/audio-dedicated bus managerissues a use prohibition to the video/audio-dedicated bus client driverwhich has issued the request for the bus 4 (Steps S110 and S111).

If the video/audio-dedicated bus client driver answers that the right touse the video/audio-dedicated bus 4 can be switched, Steps S106 and S107are performed in sequence.

In this case, the video/audio-dedicated bus manager is provided,independent of the OS. Instead, the manager may be incorporated in theOS, as one function of the OS. The programs for performing the sequenceof steps shown in FIG. 15, such as video/audio-dedicated bus manager andthe drivers, may be distributed in the form of a computer-readablerecording medium such as a CD-ROM.

As has been described above, in the present invention, different videosources can be transferred directly to the display controller,respectively from a plurality of devices which process motion-picturedata, without using the system bus. The various video sources cantherefore be displayed with high efficiency. Further, hardware orsoftware can achieve switching control so that only one device can use,at a time, the bus provided for transferring motion-picture data only,thus preventing data collision on the motion-picture bus. Still further,since the right to use the motion-picture bus is given to the lastdevice in which an enable flat has been set, motion-picture data canalways be transferred to the device which processes the very applicationthe user wants to execute.

Industrial Applicability

The present invention can provide a computer system in which differentvideo sources can be transferred directly to the display controller,respectively from a plurality of devices which process motion-picturedata, thereby to display the various video sources with high efficiency,and can also provide a method of switching video sources in the computersystem.

What is claimed is:
 1. A computer system comprising: a video port forreceiving motion-picture data; a display controller capable ofdisplaying the motion-picture data input to the video port; amotion-picture dedicated bus for transferring motion-picture data to avideo port of the display controller; and a plurality of video devicesfor processing different motion-picture sources, respectively, eachhaving an output port which is connected to said motion-picturededicated bus and from which motion-picture data is output to saidmotion-picture dedicated bus, said motion-picture dedicated busincluding a control signal line which is connected in common to saidplurality of video devices which is set into an active state by thevideo device requesting for use of said motion-picture dedicated bus,each of said video devices comprising: an output buffer for outputtingmotion-picture data from said output port to said motion-picturededicated bus; means for setting said signal control line in an activestate for a predetermined time, in accordance with a motion-picture datatransfer instruction issued from said CPU, and for allowing said outputbuffer to output the motion-picture data, after said predetermined timehas elapsed; and means for monitoring the state of said control signalline and prohibiting said output buffer from outputting motion-picturedata while said control signal remains active, whereby the video deviceset into an active state most recently is allowed to use themotion-picture data dedicated bus.
 2. A computer system according toclaim 1, further comprising means for monitoring the state of saidcontrol signal line and prohibiting said control signal line from beingset into an active state until said control signal line is released froman active state, when said motion-picture data transfer instruction isissued while the control signal remains in an active state.
 3. Acomputer system according to claim 1, wherein said output buffercomprises a three-state buffer which has a high-impedance state, andsaid means for allowing said output buffer to output motion-picture datacomprises: a register for holding enable information or disableinformation set by said CPU; and a combinatorial logic circuit forsetting said control signal for a predetermined time in response to theenable information set by said CPU in said register, setting said outputbuffer in an enable state after said predetermined time has elapsed,monitoring the state of said control signal line, and maintaining saidoutput buffer in a disable state while said control signal line remainsin an active state.
 4. A computer system according to claim 3, whereinsaid combinatorial logic circuit comprises: a pulse generating circuitfor generating a one-shot pulse signal in response to the enableinformation set by the CPU in said register; a gate circuit for settingsaid control line in an active state and resetting said output buffer inresponse to an one-shot pulse signal output from said pulse generatingcircuit; and a flip-flop circuit for setting said output buffer in anenable state in response to a signal output from said delay circuit,after a time corresponding to a width of the one-shot pulse signal haselapsed.
 5. A computer system comprising: a video port for receivingmotion-picture data; a display controller capable of displaying themotion-picture data input to the video port; a motion-picture dedicatedbus for transferring motion-picture data to the video port of thedisplay controller; and a plurality of motion-picture sources, eachhaving an output port which is connected to said motion-picturededicated bus and from which motion-picture data is output to saidmotion-picture dedicated bus, said motion-picture dedicated busincluding a control signal line which is connected in common to saidplurality of motion-picture sources which is set into an active state bythe motion-picture source requesting use of said motion-picturededicated bus, each of said motion-picture sources comprising: an outputbuffer for outputting motion-picture data from said output port to saidmotion-picture dedicated bus; means for setting said signal control linein an active state for a predetermined time, in accordance with amotion-picture data transfer instruction issued from said CPU, and forallowing said output buffer to output the motion-picture data, aftersaid predetermined time has elapsed; means for monitoring the state ofsaid control signal line and prohibiting said control signal line frombeing set into an active state until said control signal line isreleased from an active state, when said motion-picture data transferinstruction is issued while the control signal remains in an activestate; and means for monitoring the state of said control signal lineand prohibiting said output buffer from outputting motion-picture datawhile said control signal remains in an active state, whereby themotion-picture source to which a picture-image data transfer instructionis most recently issued from said CPU is allowed to use themotion-picture data dedicated bus.
 6. A computer system comprising: avideo port for receiving motion-picture data; a display controllercapable of displaying the motion-picture data input to the video port; amotion-picture dedicated bus for transferring motion-picture data to thevideo port of the display controller; and a plurality of motion-picturesources, each having an output port which is connected to saidmotion-picture dedicated bus and from which motion-picture data isoutput to said motion-picture dedicated bus, said motion-picturededicated bus including a control signal line which is connected incommon to said plurality of motion-picture sources which is set into anactive state by the motion-picture source requesting for use of saidmotion-picture dedicated bus, each of said motion-picture sourcescomprising: an output buffer for outputting motion-picture data fromsaid output port to said motion-picture dedicated bus; means for settingsaid signal control line in an active state for a predetermined time, inaccordance with a motion-picture data transfer instruction issued fromsaid CPU, and for allowing said output buffer to output themotion-picture data, after said predetermined time has elapsed; andmeans for monitoring the state of said control signal line andprohibiting said output buffer from outputting motion-picture data whilethe control signal remains in an active state, wherein the time forwhich said control signal line is set in an active state in accordancewith an motion-picture transfer instruction supplied from said CPU isdifferent for each motion-picture source, and the motion-picture sourceto which the longest time is assigned is allowed to use themotion-picture data dedicated bus before any other motion-picturesource.
 7. A computer system according to claim 6, wherein said meansfor allowing said output buffer to output motion-picture data comprises:a programmable pulse generating circuit for setting different pulsewidths for said motion-picture sources, respectively, in response to theenable information set by said CPU in said register; a gate circuit forsetting said control line in an active state and resetting said outputbuffer in response to a pulse signal output from said pulse generatingcircuit; a programmable delay circuit for delaying a pulse signal outputfrom said pulse generating circuit by different periods for saidmotion-picture sources, respectively; and a flip-flop circuit forsetting said output buffer in an enable state in response to a signaloutput from said delay circuit, after a time corresponding to a width ofthe pulse signal has elapsed.
 8. A computer system comprising: a videoport for receiving motion-picture data; a display controller capable ofdisplaying the motion-picture data input to the video port; amotion-picture dedicated bus for transferring motion-picture data to thevideo port of the display controller; a plurality of motion-picturesources, each having an output port which is connected to saidmotion-picture dedicated bus and from which motion-picture data isoutput to said motion-picture dedicated bus; and means for selecting oneof the motion-picture sources, from which motion-picture data is to betransferred to the display controller by using said motion-picturededicated bus, thereby selecting the video device which uses saidmotion-picture dedicated bus, said selecting means comprising: means formanaging condition in which said motion-picture sources use saidmotion-picture dedicated bus; means for identifying the motion-picturesource now using the motion-picture dedicated line, in response to arequest for use of said motion-picture dedicated bus, supplied from adriver program controlling the motion-picture source, and forcommunicating with the driver program controlling the motion-picturesource, thereby determining whether the motion-picture source now usingthe motion-picture dedicated bus is able to release said motion-picturededicated bus; means for issuing a permission for use of saidmotion-picture dedicated bus to the driver program which has issued therequest for said motion-picture dedicated bus, when the motion-picturesource is able to release the motion-picture dedicated bus.
 9. Acomputer system according to claim 8, wherein said means for managingcondition in which said motion-picture sources use said motion-picturededicated bus has a management table for managing the use condition ofsaid motion-picture dedicated bus for each of said motion-picturesources, and refers to the management table, thereby to identify themotion-picture source now using said motion-picture dedicated bus.
 10. Acomputer system according to claim 9, wherein when a PC card isconnected to or disconnected while the computer system is operating,said management means is notified of the connection or disconnection ofthe PC card by a card service driver program, determines from attributeinformation of the card whether the card is able to use themotion-picture dedicated bus, and adds the device to or delete thedevice from the management table.
 11. A method of switching videosources in a computer system comprising a video port for receivingmotion-picture data, a display controller capable of displaying themotion-picture data input to the video port, a motion-picture dedicatedbus for transferring motion-picture data to the video port of thedisplay controller, and a plurality of motion-picture sources, eachhaving an output port which is connected to said motion-picturededicated bus and from which motion-picture data is output to saidmotion-picture dedicated bus, said method comprising the steps of:managing condition in which said motion-picture sources use saidmotion-picture dedicated bus; identifying the motion-picture source nowusing said motion-picture dedicated bus in response to a request for useof said motion-picture dedicated bus, supplied from a driver programcontrolling the motion-picture source, and communicating with the driverprogram to determine whether the motion-picture source using themotion-picture dedicated bus is able to release the motion-picturededicated bus; and issuing a permission for use of said motion-picturededicated bus to the driver program which has issued the request forsaid motion-picture dedicated bus, when the motion-picture source isable to release the motion-picture dedicated bus.